1. Field
Example embodiments in general are directed to a method and system for creating a combined timing waveform from a max ASCII timing report and a min ASCII timing report for an application specific integrated circuit (ASIC) or field programmable gate array (FPGA), a method of converting an ASCII timing report output from a STA tool to a timing waveform to evaluate the behavior of an electrical signal in an ASIC or FPGA, a method of determining multicycle path (MCP) max and min values to a design engineer for a given external port or internal pin of an ASIC or FPGA, and a method of verifying accuracy of a min MCP value for a given external port or internal pin of an ASIC or FPGA.
2. Related Art
FIG. 1 is a block diagram of a conventional art ASIC timing closure loop. In a typical ASIC design flow, the closed loop 10 of FIG. 1 governs the ASIC design practice. The closed loop 10 in general includes a series of five stages: a layout stage 11, STA (Static Timing Analysis) stage 12, RTL/synthesis stage 13, ECO (Electronic Change Order) stage 14 and timing constraints stage 15. For purposes of brevity the STA stage 12 is discussed in more detail hereafter.
One of the most time consuming stages in ASIC timing closure loop is the STA stage. This is due primarily to two reasons. First, many timing reports are generated by a “STA tool” and need to be analyzed by the ASIC design engineer. Secondly, the STA stage is the crucial junction within the loop 10, thus the correct course of action needs to be decided through analysis of such timing reports.
A general definition of STA may be understood as the ability to measure and analyze different timing paths within an electronic device, whether these timing paths meet predefined timing budgets allocated by the ASIC design engineer. The timing path is defined as the timing distance that an electrical signal travels between any two specific points in the electronic device. A timing path has as attributes a start point, end point, max path and min path. The start point denotes the beginning of the timing path; the end point the end of timing path. The maximum timing path is defined as the longest path between start point and end point, and the minimum timing path is defined as the shortest path between start point and end point. The timing path is measured in fractions of a second. The most common measurement unit is the nanosecond ( 1/10e9 of a second), denoted by the abbreviation “ns”.
A typical STA session requires reviewing timing reports related to the following topics:                Clocks definitions;        Check timing;        Case analysis;        Inter clocks slacks;        Intra clocks slacks;        IO definitions;        IO slacks;        False timing paths;        Multi-cycle timing path;        Asynchronous slacks;        Clock gating slacks;        Exceptions considered;        Exceptions ignored;        Cross clocks timing paths; and        Specific timing paths.        
The amount or size of the timing reports can be significant (in a range of 10-100 Gbyte of ASCII timing reports, depending on the size of ASIC/FPGA, for any run of the STA tool) since it is desired to detect potential design or manufacturing flaws, and all the above report types need to be generated and analyzed for all possible PVT (Process, Voltage, Temperature) corners under which the ASIC should function. Further, ASCII (i.e., “plain text”) representation of timing reports is not intuitive and can be difficult to visualize. This often overloads the ASIC design engineer, who needs to go through and analyze many of these reports.